Firefly Programmer's Reference Manual

This document provides a comprehensive technical guide for programmers working with the Firefly system. It details the architecture of the Firefly, which is a multi-processor system featuring five processor-cache subsystems and a shared main memory. Key sections cover:

• Cache/Virtual Memory Subsystem: Operation of cache consistency, virtual-to-real address translation, and memory interface specifics.
• M-bus Communication: Protocols for inter-processor communication, reset modes, and cache control.
• I/O and Miscellaneous Functions: Programming details for specific peripherals, including the interval counter, serial I/O (mouse/keyboard/UART), an encryption chip, the clock chip, and Q-bus interface handling.

The manual is intended for those familiar with the 68010 architecture and includes detailed memory layouts and communication protocols for various onboard components.