KB11-C Processor Manual

This document, the KB11-C Processor Manual (EK-KB11C-TM-001), serves as the primary technical reference for the KB11-C Central Processor Unit in the PDP-11/70 system. The manual is structured functionally to aid in on-site troubleshooting and repair, covering key processor concepts such as microprogramming, pipelining, and memory management.

Key contents include: - Block Diagrams and Concepts: Introduction to the system architecture. - Processor Logic: Detailed analysis of instruction decoding, data paths, control registers, timing, data transfers, and trap/interrupt handling. - Memory Management: Detailed explanation of address space, relocation, and protection mechanisms. - Cache Architecture: Deep dive into the PDP-11/70 Cache, its operation, and interaction with the processor. - Console Operation: Guidelines for system control and maintenance using the PDP-11/70 console. - Engineering Appendices: Detailed block diagrams for system data and address paths.

It is recommended to be used in conjunction with the PDP-11/70 Engineering Print Set for detailed signal tracing.