Interlocked Memory Instructions for Alpha Compilers

This document outlines stricter requirements for interlocked memory instructions (LDxL and STxC) on Alpha 21264 (EV6) processors. Non-compliant code that previously functioned may fail on these newer systems, leading to synchronization loss or infinite loops. Developers should use the SRM_CHECK tool to analyze executables for potential violations, such as memory operations or branches between load-locked and store-conditional instructions. Issues can generally be resolved by recompiling with updated compiler versions, though some cases may require source code modifications to eliminate forbidden branch or memory patterns between interlocked instructions.