Field Change Order Instructions for Asr4x00 B3002 and B3004 CPU

This document outlines the field change order (FCO) procedure for addressing a specific bug in the VCTY ASIC on AlphaServer 4000/4100 CPU modules (B3002-AB and older B3004-xx). The bug can cause Real-Time applications running in an OpenVMS V7.1 SMP environment to hang or experience performance slow-downs due to instruction reordering that leads to a hardware loop. The solution requires replacing affected CPU modules with newer revisions (B3004-xx C0x or higher) or with B3005-xx CPU modules. The document provides detailed parts information, including kit numbers, as well as step-by-step removal and replacement instructions, emphasizing electrostatic discharge (ESD) safety and system verification procedures.