PDP-8, 8/I Memory Parity Checkerboard

This document provides the diagnostic procedure for the PDP-8, 8/I Memory Parity Checkerboard. It details the setup, loading, and execution requirements for testing 4K memory systems. The diagnostic utilizes specific switch register settings to write and verify parity patterns in the memory core, flagging parity errors if the hardware fails to skip as expected during an SNPE instruction. The document includes operational instructions, error halting codes, and a full program listing for both Low End and High End memory configurations.