A PDP-8 Floating Point Software Package Simulator

This document describes a simulator developed by Colorado State University that allows existing PDP-8 floating point programs to run on systems equipped with an FPP-12 Floating Point Processor. By using this simulator, operators can achieve significantly faster execution rates for floating point instructions and functions compared to conventional software packages, while also utilizing less core memory and gaining 48-bit precision. The simulator is composed of three units: the Basic FPP-12 Simulator (FPPSIM), the FPP-12 Simulator Patch (PTCHSIM), and the FPP-12 Simulator I/O Controller (IOCNTRL). The document provides details on the simulator's structure, instruction set, core requirements, and instructions for assembly and implementation.