DECchip 21164-AA (EV5 CPU)

This document, the functional specification for the DECchip 21164-AA (EV5 CPU), provides a comprehensive overview of its microarchitecture and external interfaces. Key sections include:

• Introduction: High-level overview of chip features, including support for Alpha architecture, demand-paged memory management, and on-chip caches (Icache, Dcache, Scache).
• Micro-Architecture: Detailed breakdown of functional units (Ibox, Ebox, Mbox, Cbox, Fbox), pipeline organization, and instruction issue rules.
• PALcode and IPRs: Information on processor states, PALcode opcodes, and internal processor registers (IPRs) used for managing chip functionality and error handling.
• External Interface: Details on the system interface, including command protocols, cache coherence, and memory regions.
• Reset and Initialization: Procedures for power-up and reset sequencing.
• Error Handling: Strategies for managing parity and ECC errors in caches and memory.
• Test Interface: Descriptions of testability features, including JTAG (IEEE 1149.1) support, BIST, and serial scan operations.