EV5 CPU Chip

This document describes the design and internal operation of the EV5 CPU chip, a high-performance implementation of the Alpha Architecture, dating from February 1992. It covers the functional units including the Ibox (instruction fetch and control), Ebox (integer execution), Fbox (floating-point execution), and Mbox (memory management and cache control), as well as the cache subsystem and the interconnect signals required for their operation.