EV6 Chip Specification

This document is the second revision of the EV6 chip specification, containing critical design and architectural details for the third-generation implementation of Digital's Alpha RISC architecture. It covers:

• Architecture: Detailed internal structure including the Ebox (integer execution), Fbox (floating-point execution), Ibox (instruction fetch, issue, and retire), Mbox (memory reference), and Cbox (cache and system interface).
• Pipeline Organization: A breakdown of the pipeline stages from instruction fetch to retire, including branch prediction and replay traps.
• Memory & I/O: Comprehensive rules for memory and I/O access, cache organization, coherence protocols, and memory barriers.
• Electrical & System Interfaces: Detailed specifications for the System and Bcache ports, including timing, signal lists, and clocking requirements (with specific focus on clock forwarding).
• Privileged Code: Definitions for PALcode instructions and registers.
• Error Handling: Mechanisms for detection and correction of parity and ECC errors in caches and system ports.