21464

This document provides a comprehensive technical overview and microarchitectural specification for the Alpha 21464 (EV8/Arana) microprocessor. It covers the following key areas:

• Architecture Overview: Detailed breakdown of the instruction unit (Ibox, Pbox, Qbox), execution unit (Ebox, Fbox), memory unit (Mbox), and external interfaces (Cbox, Rbox, Zbox).
• Instruction Fetch Unit (Ibox): Describes instruction stream bandwidth, branch prediction (including history-based jump target prediction), the collapsing buffer, and memory dependence prediction using store sets.
• Instruction Issue and Retire: Explains the Qbox instruction queue, scheduling rules, and retirement logic.
• Execution Units: Details on the integer units (Ebox), floating-point units (Fbox) including paired single-precision support, and memory execution (Mbox) with cache coherence.
• Memory Management: Covers the instruction and data translation buffers (ITB/DTB) and support for superpages.
• Internal Processor Registers (IPR): Comprehensive list and definition of processor-specific registers used for configuration and status monitoring.
• Cache Coherence Protocol: Describes the directory-based CC-NUMA coherence protocol and its implementation within the Cbox.
• Hardware Debug and Testability: Outlines features for debug (Scan, Trace Bus, Trigger Logic) and testing (BIST/BISR).
• Miscellaneous Interfaces: Includes information on the GIO port and Rambus interface.