Processor Flow Chart

This document provides detailed technical specifications for the PDP-8/E processor, including a comprehensive processor flow chart and timing diagrams. It covers the following key areas:

• Processor Flow Chart: Detailed visual logic for the Fetch, Defer, Execute, and Direct Memory Access (DMA) cycles.
• Timing Diagrams: Detailed clock and control signal timing diagrams for fast cycles, slow cycles, and external I/O cycles, including signal strobe generation and memory signal timing.
• Logic Diagrams: Detailed circuitry information for major registers (KK8/E), including back-connector signal connections, register bus mappings, and timing generation circuitry.