PDP-8/E

This document provides a detailed technical description of the PDP-8/E processor. It is divided into several functional sections:

• System Introduction: Provides a block diagram of the processor and explains the OMNIBUS signal architecture.
• System Flow Diagrams: Details the major states (FETCH, DEFER, EXECUTE, DMA) and manual operations like Start-Up and Stop.
• Timing Generator: Explains the M8330 module, its timing states, and the logic behind slow and fast cycles.
• Memory System: Details the MM8-E memory system, including core selection, read/write cycles, and the function of sense amplifiers and inhibit drivers.
• Central Processor: Describes the M8300 and M8310 modules, detailing how instructions are manipulated and gated through the system.