Alpha AXP System Reference Manual

Summary

This document is the "Alpha AXP System Reference Manual" (Version 6), which provides a comprehensive architectural specification for the Alpha AXP 64-bit load/store RISC architecture.

Key aspects covered in the manual include:

• Architectural Overview: Describes the Alpha AXP design principles, focusing on high clock speed, multiple instruction issue, and multiprocessor support. It outlines the 64-bit architecture, simple 32-bit instruction length, and the lack of implementation-specific hazards.
• Data Formats and Addressing: Details addressing modes, data types (byte, word, longword, quadword), and floating-point formats (VAX and IEEE).
• Instruction Set and Formats: Categorizes and describes the instruction formats (Memory, Branch, Operate, PALcode) and provides detailed descriptions of the instruction set, including integer arithmetic, logical, shift, byte-manipulation, and floating-point operations.
• System Architecture and Programming: Explains physical address space characteristics, memory coherency, read/write ordering, and the handling of arithmetic traps and shared memory in multiprocessor systems.
• PALcode Architecture: Describes the Privileged Architecture Library (PALcode) mechanism, which provides OS-specific primitives for system functions (like context switching and memory management) without requiring microcode.
• Console Interface and Bootstrapping: Provides specifications for console operations, the Hardware Restart Parameter Block (HWRPB), console callback routines, and system bootstrapping processes across different environments.
• Operating System Support: Contains sections detailing the architectural requirements and PALcode instruction descriptions specifically for OpenVMS AXP, DEC OSF/1, and Windows NT AXP.
• Conformance and Appendices: Includes details on IEEE floating-point conformance, instruction summaries, and information on implementation-dependent functionality and waivers.