82345 Data Buffer

This document describes the 82345 Data Buffer, which is part of the 82340DX three-chip set alongside the 82346 System Controller and 82344 ISA Bus Controller. The 82345 facilitates data routing between the CPU bus, memory data (MD) bus, peripheral data (XD) bus, and system data (SD) bus in 386 DX-based personal computers.

Key features include: - Support for posted cache writes and non-posted MD bus writes. - Parity generation and checking for MD bus operations. - Data width conversion (8-bit to 16/24/32-bit, or 16-bit to 32-bit) without forcing the 386DX out of pipelined mode. - Flexible system DRAM placement on either the MD or D bus. - Byte swapping capabilities on the SD bus. - A high-impedance tri-state mode (TRI#) for board-level testing.

The document also provides comprehensive signal descriptions categorized by interface (CPU, Cache, System Controller, Bus Controller, and Buffer), along with pin configuration and electrical specifications.