A Memory Subsystem for the i486™ CPU including Second Level Cache

The document, an Intel Application Note (AP-447) from November 1990, provides detailed technical guidance for designing a memory subsystem for the i486 CPU. The design incorporates two primary performance-enhancing techniques: memory interleaving to support burst cycles and a write-posting mechanism to reduce write cycle latency. Additionally, the system includes an optional second-level cache (utilizing the 485Turbocache module) to further improve memory access rates. The document covers functional block overviews, control logic implementation using Programmable Logic Devices (PLDs), and specific memory interface timing considerations. It includes schematics and PLD code examples to demonstrate how to achieve zero-wait-state performance at 25 MHz and 33 MHz.