Alpha 21264/EV67 Microprocessor

This manual describes the architecture, internal organization, and interfaces of the Alpha 21264/EV67 microprocessor. Key sections cover: - Internal Architecture: Explains the Ibox, Ebox, Fbox, Mbox, and Cbox units. - Cache and External Interfaces: Details system port transactions, Bcache operations, and cache coherency. - Internal Processor Registers (IPR): Provides detailed register definitions. - Privileged Architecture Library Code (PALcode): Describes PALmode, entry points, and restrictions. - Initialization and Configuration: Outlines power-up reset flows, configuration sequences, and Bcache/array setup. - Testability and Diagnostics: Covers IEEE 1149.1, SROM load, and built-in self-test (BiST).