Interface Between a Pair of Processors, Such as Host and Peripheral-Controlling Processors in Data Processing Systems

This document describes a patented interface mechanism designed for data processing systems to allow for communication between a host processor and an intelligent peripheral controller. The interface utilizes a set of shared data structures in a dedicated memory region consisting of command and response ring buffers. These rings allow asynchronous, bi-directional communication between the two processors. By employing an "ownership" bit or byte in each ring entry to control access to the buffers, the system ensures proper command sequencing and avoids race conditions, eliminating the need for complex hardware interlock mechanisms on the I/O bus. This approach minimizes processor interrupt delays and allows the host and controller to operate at different speeds, while also providing a verification method for the controller's correct operation during initialization.