SHAC: Single Host Adapter Chip

This document is the engineering specification (Version 4.0, dated September 1989) for the Single Host Adapter Chip (SHAC). The SHAC is a VLSI-based SCA (Systems Communications Architecture) port designed to interface VAX host systems to the Digital Small System Interconnect (DSSI) bus. It functions by translating between the host's high-speed bus and the DSSI bus using standard CI protocols.

Key sections of the document include: * Pinout and Signal Descriptions: Covers the CP_bus, DSSI bus, power, and testing signals. * Registers: Defines host-addressable registers, including both standard CI Port registers and SHAC-specific registers for maintenance and control. * Host-SHAC Communication: Details initialization sequences, supported CI opcodes, and error handling. * Bus Operations: Describes the logical interactions between the SHAC and the host bus (DMA cycles, CPU cycles) and the DSSI bus (phase sequences, arbitration, and retries). * Appendices: Include related documents, the fair-arbitration scheme for DSSI, shared host memory structures, and comprehensive testing features and error code definitions.