Interface Between a Pair of Processors, Such as Host and Peripheral-Controlling Processors in Data Processing Systems

This document is U.S. Patent 4,449,182, titled 'Interface Between a Pair of Processors, Such as Host and Peripheral-Controlling Processors in Data Processing Systems'. The patent details an interface mechanism designed for data processing systems where a host processor and an intelligent peripheral controller (e.g., for mass storage) share a memory region. To facilitate this communication over buses lacking hardware interlock features, the invention uses a set of data structures in the host's memory, organized into command and response 'rings'. These rings, combined with an 'ownership' byte protocol, allow the processors to operate at independent speeds while avoiding race conditions and minimizing host processor interrupts.