System for Interrupt Arbitration

This document outlines a patent for a data processing system featuring an improved arbitration arrangement for handling processor interrupts. The system utilizes a common bus where each connected unit has a pre-assigned priority. When an input/output or other unit requires service, it requests an interrupt from the processor. Upon receiving a grant, the interrupting unit must perform an arbitration operation on the system bus to gain control, ensuring that higher-priority bus transfers (such as memory access) can proceed. Once the unit secures bus control, it transfers an interrupt vector—which identifies the location in memory of the appropriate interrupt service routine—to the processor. The patent includes detailed flowcharts, timing diagrams, and schematic diagrams describing the control logic, signal request paths (BR/BG), and bus arbitration processes (DBBZ) required for this mechanism.