Phase Locked Loop with Bandwidth Ramp

This document describes a phase locked loop (PLL) design that enhances performance for data processing systems like disk drives. The PLL features an input control to vary its response time, adjusting the loop bandwidth monotonically. By decreasing the bandwidth slowly, the design achieves faster lock acquisition and better noise immunity compared to conventional approaches that abruptly switch bandwidth, which can cause transients and data recovery errors. The invention allows the preamble portion of an input signal to be shortened, increasing usable storage capacity.