Memory Checkerboard

The Memory Checkerboard program is designed to test the PDP-1 memory for read-out errors. It functions by filling memory with specific 'worst-case' noise patterns arranged in a checkerboard array to stress the sense windings. The program includes five major routines—pattern construction, control, write, check, and error—to perform thorough testing.

Key features and procedures include: * Operating Options: Users can select different noise patterns (via sense switches), limit the memory range to be tested, exclude specific core planes (via test word switches), and control error behavior. * Operational Modes: The program can exist in either a low-core or high-core configuration to ensure all memory locations are tested. * Error Handling: The program can be configured to either halt upon encountering an error or ignore errors to allow for oscilloscope analysis of recurring issues. * Operational Procedures: Detailed instructions are provided for loading, running, setting limits, and restarting the program following an error halt.