Project Jupiter 2nd Levels

This document provides a detailed collection of technical diagrams and timing schematics for the DEC KC10/2080 CPU. It covers several key subsystems, including:

• CPU Pipeline: Flow diagrams for instruction fetching and processing.
• CPU Partitioning: High-level functional breakdown of the FPA, EBOX, IBOX, and MBOX units.
• Timing & Clocking: Detailed clock cycle and instruction timing diagrams (22ns, 44ns, 66ns).
• Logic & Interface Schematics: Extensive diagrams for the EUNIT/MBOX interface, FRU priority encoders, IBOX/EBOX/FPA clock control mechanisms, and data path logic.
• Prefetch Systems: Detailed flow and logic for the LRF (LRF read-write timing) and IBOX prefetch streams (Streams A, B, C).
• Other Components: Includes detailed logic for the Multiply Array (FPA), Modulo 3 checking, and various EBOX/IBOX internal data paths.