A Low-Cost, Space-Efficient PDP-10

The provided document is a 1983 technical proposal and accompanying internal cost memorandum for the development of a "departmental" PDP-10 processor, internally referred to as the "KD10" or "Project MICRO20."

The goal of the project was to create a cost-effective, space-efficient PDP-10 system capable of supporting 20–32 users. To minimize engineering time and risk, the system design relied on upgrading the existing KS10 (2020) architecture, reusing corporate standard buses (Unibus), and utilizing existing peripherals. Key technical specifications included:

• Support for 30-bit extended addressing.
• A CPU fitting on two extended hex modules using AMD2901 components.
• Memory capacity of up to 4 Mwords with ECC support.
• Packaging designed to fit within existing 11/750 or RA81 cabinets.

The proposal also outlined a development timeline of approximately 18 months, emphasizing that software and diagnostic resources would be minimized by maintaining hardware-software interfaces identical to the KS10. The cost analysis memorandum provides a breakdown of projected material, labor, and overhead costs for the project components, aiming for an entry-level system price range of $15,000 to $20,000.