TOPS-10/20 Sales Training

This document is a student guide for the TOPS-10/20 Sales Training program, focusing on the architecture and implementation of the KL processor family. It details the evolution from previous Digital architectures, the use of microprogrammed instruction sets, the memory subsystem (including cache and virtual memory management), and the role of the PDP-11 front-end system. Additionally, the guide covers I/O bus architectures, including MASSBUS and UNIBUS, and provides a historical context of Digital’s timesharing environments and system design philosophy.