Dolphin Clocking - Control and Distribution Specification

This document specifies the architecture and logic for the Dolphin processor's clock distribution system. It details the use of a 60 MHz master VFO oscillator that can be adjusted via a console control register. The clock signal is divided to provide a 30 MHz bus clock and distributed through a tree structure using Clock Distribution MCAs. The specification includes information on clock initialization, phase management (A/B phase), clock control functions (start, stop, burst, half-step), and error handling through parity checks and error registers. It also includes pin/signal descriptions and skew calculations for different module configurations.