IBox/EBox Functional Specification

This document outlines the design of the Dolphin CPU, which utilizes a tightly coupled multiprocessor architecture featuring two distinct microcoded machines: the IBOX and the EBOX. The IBOX is responsible for instruction fetches and effective address calculations, while the EBOX handles computation and result storage. The document covers the rationale for this split (citing instruction frequency benchmarks), the data path designs for both processors, the interface mechanisms (including interlocks and 'last' registers for communication), and timing considerations for achieving performance goals compared to the KL10 architecture.