PDP-10 MX10 Memory Multiplexor

This document serves as a comprehensive maintenance manual for the MX10 Memory Data Multiplexor, an optional component for PDP-10 computer systems that enables the connection of up to eight peripheral processors (such as the DF10 Data Channel) to the memory system.

Key contents include: * General Information: Overview of system integration and specifications. * Installation: Guidelines on interconnections, cable locations, and bus configuration. * Operation: Functional description of the indicator panel and its utility for maintenance. * Principles of Operation: Detailed logic flow for Power-On, Request operations, Memory Read/Write cycles, and Read-Modify-Write cycles. * Maintenance: Troubleshooting procedures including off-line testing, use of the MX10T Off-Line Tester, margin tests, and a complete list of spare parts. * Engineering Drawings: A collection of block schematics, logic diagrams, and module utilization charts to support technical servicing.