Logical and Physical Core Allocation Routines

This document provides the source code listing and assembly documentation for the 'CORE1' routine (V414), which is responsible for logical and physical core memory allocation on a PDP-10 system. The routines manage memory in 1K blocks using a 'CORTAB' bit table to track memory status (monitor usage, user usage, or non-existent memory). Key features documented include:

• Core Allocation: Mechanisms for assigning memory, updating 'JBTADR' tables, and handling hardware relocation/protection.
• Core Shuffling: A routine designed to periodically check and shuffle jobs in memory to optimize layout and minimize fragmentation, dependent on device status.
• Core Management: Specific routines ('CORE0', 'CORE1', 'KCORE1', 'CORGET') for flushing, reassigning, and managing memory for various system commands (e.g., RUN, GET, KJOB).
• Error Handling: Logic for handling insufficient memory scenarios and interacting with the system swapper.

The document includes extensive technical notes, detailed assembly code, and a complete symbol table for the routines.