This document is a technical collection of schematics detailing the Writeable Control Store (WCS) for the LSI-11 computer system. It includes diagrams for the MIB interface transceivers, DAL bus timing and selection logic, MIB data out selection, RAM address multiplexing and latching, data RAM arrays, and trace mode logic. The document includes a note indicating that the design is a 'CAUTION CHANGE IN-PROCESS'.
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