This document serves as a comprehensive technical guide for the Digital Equipment Corporation's PDP-11 computer system. It details the system architecture, focusing on the Unibus structure, the KAl1 processor, and the memory organization.
Key contents include: - System Overview: A look at the modular design, asynchronous operations, and priority interrupt system. - Addressing Modes: An in-depth explanation of PDP-11 addressing, including general register, indexed, autoincrement/autodecrement, stack, and relative addressing. - Instruction Set: A detailed breakdown of instructions, including double-operand, single-operand, branches, and traps, with notation and timing information. - Programming & Peripherals: Instructions for programming standard peripheral devices like the Teletype (model LT33) and High-Speed Paper Tape reader/punch (model PC11). - Interface & Configuration: Technical details on interfacing with the Unibus, bus arbitration, and configuration/installation planning for various PDP-11 models. - Appendices: Quick-reference tables for the instruction repertoire, addressing summary, and memory address maps.
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