11/60 Microprogramming Specification

This document serves as a draft technical specification for the microprogramming of the PDP-11/60 processor. It is intended for experienced assembly-language programmers and hardware engineers.

Key contents include: * Datapath Overview: A detailed description of the 11/60 datapath, including scratchpads (ASP, BSP, CSP), the D-register, ALU, and shifting mechanisms (Shift Tree and Shift Register). * Microinstruction Sequencing: Explanation of the chained sequencing technique used by the 11/60 and the microinstruction branching logic. * Processor Control: Insights into the inner machine operations, including memory control, the Cache/KT section, the Bus Control section, and the Writable Control Store (WCS) option. * Usage Guidelines: Practical advice on using the WCS option, including entry points and the use of the Transfer Micro Store (TMS) ROM for routines. * Appendices: A glossary of terms, the Instruction Set Processor (ISP) notation used, a bibliography, and detailed listings of resident microcode and dispatch tables.