This document provides a technical specification for the KDJ11-B CPU module. It covers the processor architecture, including the J-11 chipset, instruction set, and instruction timing. The guide details the environmental requirements, memory management features, 8K-byte cache system, and the Private Memory Interconnect (PMI). Furthermore, it describes hardware-detected error handling, power-up/down protocols, the Micro-ODT console, and the boot and diagnostic facilities. Several appendices list instructions, module pinouts, and system-specific differences.
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