Introduction to the PDP-11

This workbook is designed to teach students the fundamentals of priority control within the PDP-11 architecture. It covers the following key topics:

• Priority Structure: Explains the 2D priority system consisting of vertical levels (NPR, BR7-BR4) and horizontal priority (bus latency/chaining).
• Bus Control: Details how the priority arbitration logic functions as an umpire to handle simultaneous requests, including the role of Non-Processor Requests (NPR) for DMA and Bus Requests (BR) for CPU-assisted interrupts.
• Configuration & Factors: Outlines critical considerations for assigning priorities, such as operating speed, data recovery requirements, and service needs.
• Operational Procedures: Describes the interactions between devices and the CPU during bus requests, grants, and transfers.

Included in the document are learning objectives, a course map, review material with key concepts, a list of additional resources (including specific sections of the Processor and Peripherals handbooks), and a self-scoring test with questions to assess student understanding of the material.