J-11 Control Chip

The J-11 Control Chip Specification (21-17679-00) details the internal architecture and functional characteristics of the control chip utilized in high-performance PDP-11 processor systems. The control chip contains microprogram sequence logic, 1280 words of microprogram storage (divided between PLA and ROM sections), and various functional blocks such as the next address logic, counter logic, prefetch logic, and interrupt service logic. The document includes technical specifications for internal busses, state sequencing, interface signals, DC/AC characteristics, and test mode operations. It also provides a revision history and detailed timing diagrams for chip operations.