Data Chip Specification

This document specifies the internal organization and design of the J-11 Data chip, a MOS/LSI component of a chip set used to implement a high-performance PDP-11 processor. It includes detailed information on:

• Execution Unit (EU): Register file organization, special B-bus logic, data path, and branch/jump logic.
• Memory Management Unit (MMU): Relocation registers, memory management logic, and special registers.
• Prefetch Mechanism: Operation, fault detection, and resynchronization sequences.
• Microinstructions: Formats, opcodes, and functional descriptions.
• Interface: Input and output signals, electrical DC characteristics, and AC timing requirements.

The document provides timing diagrams for various I/O operations and detailed tables mapping instructions and register access codes.