Basic PDP-11 Description and Instruction Set

This engineering specification (ES:0001, dated 28 March 1968) details the fundamental architecture and instruction set of the PDP-11/30 system. It covers the processor's two-address machine organization, the 16-bit instruction word structure, byte-addressable memory, and the general register/accumulator configuration. The document defines the three classes of instruction formats (single, double, and triple word), explains the assembly syntax, and provides detailed operation definitions for binary arithmetic, logical operations, branching, and unary operations. It also includes appendices with an instruction summary and specific address mode configurations for the PDP-11 series.