Details of Design

This document provides early design documentation for the KA11 processor used in the PDP-11 computer, dated September 1969. It describes the primary processor components, including the 16-bit scratch pad memory, data paths, and control logic. Key sections cover:

• Processor Architecture: The data paths consist of input gates, latches, adders, and shift/rotate gating, all 16 bits wide.
• Timing: The system utilizes a 125ns square wave clock to derive a 250ns machine state period, supporting asynchronous operation with bus transmissions.
• Instruction Flow: Details on the fetch, execute, and service cycles, including how instructions are decoded and executed, and how memory and bus references are managed.
• Address Modes: A comprehensive summary of the addressing modes used in PDP-11 instructions.
• Control: Explanations of how control logic manipulates memory and bus inputs to the data paths to perform specified instructions.