Operational Details in the MUL and DIV Instructions

This design note provides an in-depth technical explanation of the MUL (multiply) and DIV (divide) instructions on the PDP-11. It details the behavior of condition codes (Z, N, V, C bits) for these operations, including overflow conditions, and clarifies the specific word order and addressing requirements for sources, destinations, and intermediate results in both register and memory operations. Furthermore, it discusses the architectural choice of the system's byte/word order and evaluates the implications of potential design alternatives on programming compatibility and performance in real-time environments.