An Instruction Set for the 18-bit PDP-K

This document, titled 'An Instruction Set for the 18-bit PDP-K' (Technical Memorandum #4, dated February 20, 1970), proposes a new 18-bit computer architecture designed to address the limitations of 16-bit systems, particularly for Pulse Height Analysis (PHA) and floating-point applications. The document outlines the instruction formats, terminology, addressing modes, and compatibility considerations. It includes detailed appendices for the proposed instruction set, byte handling, condition codes, instruction formats, and subroutine call implementation.