PDP-11 Cache Memory Scheme & Considerations

This document outlines the design considerations for implementing cache memory in the PDP-11/40 system. It defines key physical parameters to be simulated, including buffer size, block size, and various mapping algorithms such as Full Associative, Congruent, and Set Associative. The document further details placement and purging strategies, including core image update schemes (write-back vs. immediate update) and purging algorithms like Least Recently Used (LRU). Finally, it discusses the implications of cache memory within a paging and segmentation environment.