Segmentation Scheme for the PDP-11 Family

This document outlines a preliminary segmentation scheme for the PDP-11 family of computers. The primary objectives are to increase user virtual address space to 4 million bytes and physical address space to 8 million bytes, implement memory sharing and protection, provide a hardware-level definition of the 'working set' model, and enable processes to manage private I/O devices. The proposed architecture uses a 16-bit virtual address divided into a 3-bit Working Segment Field (WSF) and a 13-bit Displacement Field (DF). It details the use of Segment Descriptor Words (SDWs) stored in a Segment Table (ST), the role of the Master Control Process (MCP) in managing these resources, and mechanisms for interruptability to maintain fast response times. The scheme is designed to be compatible with or without paging.