The PDP-11 Floating Point Unit

This document outlines the design and implementation of the Floating Point Unit (FPU) as an option for the PDP-11 series of computers, specifically the PDP-11/05, 11/20, and 11/40. The FPU is designed to be a largely independent processor that offloads single and double-precision floating-point arithmetic from the main CPU, allowing for concurrent operation. The memo covers:

• Architectural Choices: Discussion on the pros and cons of connecting the FPU to the bus versus as an internal option, and operating in virtual versus physical address space.
• FPU-CPU Interaction: Details on how the FPU is initiated, including the use of JSR instructions and trap service routines to hand off control.
• Instruction and Data Formats: Comprehensive definitions of FPU instructions, their formats, and how floating-point data (32-bit and 64-bit) is represented.
• Program Status Register: A detailed breakdown of the FPU status register, its mode bits (truncate, double precision, extended precision, etc.), and condition codes.
• Appendices: Summaries of the full FPU instruction set and floating-point execution times.