Protection and Relocation for the PDP-11/40

This document, labeled as Technical Memo #29, outlines a memory management and protection implementation for the PDP-11/40. It proposes a segmentation scheme that provides a physical address space of 2^18 bytes, with a maximum active virtual address space of 2^16 bytes. The system uses an Active Segment Field (ASF) to determine which of the eight Active Segment Registers (ASR) to use for forming a physical address.

Key features include: - Use of Segment Descriptor Words (SDW) to manage segment access rights (via keys) and length. - Memory management trapping for non-resident faults and statistical tracking. - Hardware aids for recovering from segmentation faults, including support for instruction restarting. - Status registers (SSR0, SSR1, SSR2, SSR3) for tracking errors, status, and register modifications during memory operations. - Proposed implementation on two QUADS boards using specific logic chips. - Interface signal specifications for connecting the segmentation option to the processor.