MIPS IV Instruction Set

This document defines the CPU instruction set architecture for the MIPS IV processor. It provides a detailed breakdown of instruction functional groups, including load and store operations, ALU operations, jump and branch instructions, and miscellaneous operations. The document also includes comprehensive details on instruction formats, encoding, and the FPU (floating-point unit) instruction set. It further details the MIPS IV backward-compatible architecture extensions, memory access types, and pseudocode notation used to describe individual instructions.