IR Decode and Condition Codes

This document provides detailed schematic diagrams and logic documentation for the IR (Instruction Register) decode and condition code generation circuitry used in the 11/45 computer system. It includes part lists, signal descriptions, and logic maps illustrating how instructions are decoded and how condition codes (N, Z, V, C) are updated during instruction execution. The document covers multiple sheets representing various parts of the instruction processing pipeline, including trap handling and source/destination constant definitions.