This document consists of a four-page set of schematic diagrams detailing the 'Rainbow Memory Extension' circuitry. The sheets cover the following functional areas:
Sheet 1: Data buffer and parity generation/checking circuitry.
Sheet 2: Bank select logic and RAM control buffers.
Sheet 3: Refresh counter logic and DRAM address multiplexing.
Sheet 4: RAM chip array configurations (using 4164/41256 DRAM chips).