Alpha 21264/EV6 Microprocessor

This manual provides a detailed technical reference for the Alpha 21264/EV6 microprocessor, a third-generation implementation of the Alpha architecture. The document is divided into the following sections:

• Introduction: Overview of the Alpha architecture and the features of the 21264/EV6.
• Internal Architecture: Describes the hardware functions, pipeline organization, instruction issue and retire rules, memory and I/O address space, and performance measurement features.
• Hardware Interface: Contains logic symbols, signal names, functions, pin lists, and mechanical specifications.
• Cache and External Interfaces: Details the Bcache and system interfaces, including cache coherency and locking mechanisms.
• Internal Processor Registers (IPR): Lists and describes the register set.
• Privileged Architecture Library Code (PALcode): Describes the privileged macrocode used for system-specific operations.
• Initialization and Configuration: Covers the power-up, fault, and warm reset sequences.
• Error Detection and Error Handling: Details the detection and handling of ECC and parity errors.
• Electrical Data: Provides electrical characteristics, thermal management, and testability features.
• Appendixes: Include instruction summaries, boundary-scan register descriptions, and guidelines for PALcode generation.