IO Bus Sequences

This document, dated October 5, 1967, serves as a technical memorandum detailing the operational sequences of the PDP-X IO Bus. It describes the communication architecture between the central processor and peripheral devices, including both processor-initiated and device-initiated activities.

Key aspects covered include:

• Bus Architecture: The IO Bus consists of 8 bi-directional data lines and 32 control lines, categorized into outbound/inbound control, priority request, and priority grant groups.
• Operational Modes: The document defines how the processor and devices coordinate tasks, including the use of specific instructions like IOR, IOW, and IOS.
• Sequence Flowcharts: The appendix provides detailed flow diagrams for various bus operations, such as single and double-byte data input/output, interrupt handling, and channel operations (including "Add In" operations where data is added to memory).
• System Functionality: It outlines how devices signal completion of tasks via interrupts and how the processor manages these requests through a priority system.