PDP-X Processor Description

This document, Technical Memorandum #29, provides a comprehensive technical overview and architectural description of the PDP-X computer family. It outlines significant changes made since the previous version (Technical Memorandum #13), including updates to memory address space, instruction sets, trap conditions, and interrupt handling. The document covers:

• Processor Architecture: Details on instruction formats, data types (fixed and floating-point), addressing modes, and the usage of general registers.
• System Status: Definitions of the Program Status Word (PSW) and condition codes.
• Instruction Set: Descriptions of basic and extended instructions, including arithmetic, logical, character, and I/O-related operations.
• I/O System: The structure of the I/O bus, modes of data transfer (program-controlled, multiplexor, and selector channels), and peripheral controllers.
• Priority Interrupt System: Details on interrupt levels, nested operations, and how devices interface with the processor.
• Memory Protection: Specifications for the optional protection feature, including memory paging, user/monitor modes, and monitor calls.

The document also serves as a reference for assembly language conventions and provides example routines for common operations.